The SN65DSI83TPAPRQ1 DSI-to-LVDS bridge features a single-lane MIPI D-PHY receiver front-end configuration with 4 lanes per lane, each lane operating at 1Gbps, with a maximum input bandwidth of 4Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 24bpp RGB888 video streams and converts the formatted video data streams to LVDS outputs with a pixel clock ranging from 25MHz to 154MHz, providing single-link LVDS with 4 data channel).

The SN65DSI83TPAPRQ1 device supports resolutions up to WUXGA 1920 × 1200 (60 frames per second, 24bpp with reduced blanking). The SN65DSI83-Q1 device is also suitable for applications using 60fps 1366 × 768/1280 × 800 (18bpp and 24bpp). The device implements partial line buffering to accommodate data flow mismatch between DSI and LVDS interfaces.

The SN65DSI83TPAPRQ1 device is packaged in a small-outline 10mm × 10mm HTQFP (0.5mm pitch) package and operates over the –40ºC to +105ºC temperature range.

Product Specifications:

Manufacturer: SN65DSI83TPAPRQ1

Product Category: LVDS Interface ICs

RoHS: Details

Type: DSI to LVDS Bridge

Number of Drivers: 4 Driver

Number of Receivers: 4 Receiver

Data rate: 1.078 Gb/s

Input type: MIPI D-PHY

Output type: LVDS

Supply Voltage - Max: 1.95 V

Supply Voltage - Min: 1.65 V

Minimum working temperature: - 40 C

Maximum working temperature: + 105 C

Installation style: SMD/SMT

Package / Box: HTQFP-64

Qualification: AEC-Q100

Package: Reel

Development Kit: SN65DSI83EVM

Humidity Sensitivity: Yes

Working power supply current: 77 mA

Product Type: LVDS Interface IC

Series: SN65DSI83-Q1

Subcategory: Interface ICs

Unit weight: 305.600 mg