Shenzhen Meiyuxin Technology Co., Ltd. [distributing NXP microcontrollers] sells LPC55S69JBD64 Arm® Cortex®-M33 microcontrollers! ! !

LPC55S69JBD64 product description:

The LPC55S69JBD64 is an ARM Cortex-M33 based microcontroller for embedded applications. These devices include ARM Cortex-M33 coprocessor, CASPER Crypto/FFT engine, PowerQuad hardware accelerator for DSP functions, up to 320 KB on-chip SRAM, up to 640 KB on-chip flash, PRINCE module for on-the-fly flash encryption/decryption , high-speed and full-speed USB host and device interface with crystal-less operation for full-speed, SD/MMC/SDIO interface, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit multi-rate timer device (MRT), a window watchdog timer (WWDT), nine flexible serial communication peripherals (configurable as USART, SPI, high-speed SPI, I2C or I2S interface), programmable logic unit (PLU), A 16-bit 1.0 Msamples/sec ADC capable of simultaneous conversions.

The LPC55S69JBD64 ARM Cortex-M33 provides a secure foundation, providing isolation to protect valuable IP and data with TrustZone® technology. It simplifies the design and development of software-integrated digital signal processing (DSP) instructions for digital signal control systems. To support security requirements, the LPC55S6x also provides support for secure boot, HASH, AES, RSA, UUID, DICE, dynamic encryption and decryption, debug authentication and TBSA compliance.

LPC55S69JBD64 Features:

 ARM Cortex-M33 core (CPU0, r0p3):

 Operates at frequencies up to 150 MHz (device revision 1B only).

 TrustZone®, Floating Point Unit (FPU), and Memory Protection Unit (MPU).

 ARM Cortex M33 built-in nested vectored interrupt controller (NVIC).

 Non-maskable interrupt (NMI) input with selectable source.

 Serial wire debugging with eight breakpoints and four watchpoints. Includes serial wired output for enhanced debug capabilities.

 System tick timer.

 The configuration of this example includes MPU, FPU, DSP, ETM, and Trustzone.

 ARM Cortex-M33 coprocessor (CPU1, r0p3):

 Runs at CPU frequency up to 150 MHz (device version 1B only).

 This example configuration does not include MPU, FPU, DSP, ETM, and trusted zone.

 System tick timer.

 Provide the CASPER Crypto coprocessor to implement various hardware acceleration functions required by certain asymmetric encryption algorithms, such as Elliptic Curve Cryptography (ECC).

 PowerQuad hardware accelerator for (fixed-point and floating-point unit) CMSIS DSP supports functions of SDK software API to execute ARM CMSIS instructions faster.