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Sales ATSAMA5D24C-CUR Microprocessor - MPU

Time:2023-03-06   Views:

Shenzhen Meiyuxin Technology Co., Ltd. [distributing microchip products] sells ATSAMA5D24C-CUR microprocessor - MPU quality assurance brand new original! !


Product Description:

SAMA5D2 is a high-performance, ultra-low-power Arm Cortex-A5 CPU-based embedded microprocessor (MPU) running at up to 500 MHz, supporting a variety of memory, such as DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, LPDDR3, QSPI and e.MMC flash, and SLC/MLC parallel NAND flash up to 32-bit ECC. It integrates an Arm NEON SIMD engine for accelerating multimedia and signal processing, a configurable 128 KB L2 cache, and a floating-point unit (FPU) for high-precision calculations. The device has an advanced user interface and connectivity peripherals. Advanced security is provided by powerful cryptographic accelerators powered by ArmTrustZone® technology that secures access to memory and sensitive peripherals through multiple hardware features to secure memory contents, authenticate software, detect physical attacks, and prevent information disclosure during code execution.


The SAMA5D2 has an internal multilayer bus architecture associated with 2 x 16 DMA channels and a dedicated DMA processor overhead for communication and interface peripherals required to ensure uninterrupted data transfers.


The comprehensive set of peripherals includes an LCD TFT controller with overlay composition for hardware accelerated graphics, image sensor controller, audio support via I2S, SSC, stereo class D amplifier and digital microphone. Connectivity peripherals include 10/100 EMAC, USB, CAN, FLEXCOM, UART, SPI and two QSPIs, SDIO/SD/e.MMC and TWI/I2C.


Protect code and data by automatically scrambling memory and Integrity Check Monitor (ICM) to detect any modification of memory contents. SAMA5D2 also supports the execution of encrypted code (QSPI or part of DDR) with "on the fly" encryption and decryption process. With its Secure Design Architecture, Cryptographic Acceleration Engine and Secure Bootloader, SAMA5D2 is an ideal solution for point-of-sale (POS), IoT and industrial applications requiring device authentication, anti-cloning, data protection and secure communication.


The SAMA5D2 has three software selectable low power modes: Idle, Ultra Low Power (ULP) and Backup. In idle mode, the processor is stopped while all other functions can keep running. In ULP0 mode, the processor is stopped, while all other functions are clocked at 512 Hz, and interrupts or peripherals can be configured to wake up the system based on events, including partial asynchronous wakeups.


In ULP1 mode, all clocks and functions are stopped, but some peripherals can be configured to wake up the system based on events, including partial asynchronous wakeups. In backup mode, the RTC and wake-up logic are active. Backup mode can be extended to have DDR in self-refresh mode.


The SAMA5D2 also includes an event system that allows peripherals to receive, respond and send events in active and idle modes without processor intervention.



Features:

• ARM Cortex-A5 core

– Armv7-A architecture

– Arm trust zone

– Neon™ media processing engine

– Up to 500 MHz

– ETM/ETB 8 KB

• memory architecture

– Memory Management Unit (MMU)

– 32 KB L1 data cache, 32 KB L1 instruction cache

– 128 KB L2 cache configurable for use as internal SRAM

– One 128 KB scrambled internal SRAM

– A 160 KB internal ROM

• 64 KB of scrambled and maskable ROM embedded bootloader/secure bootloader

• 96 KB of unencrypted, non-maskable ROM for NAND flash BCH ECC table

– High-bandwidth scrambleable 16-bit or 32-bit Double Data Rate (DDR) multi-port dynamic RAM controller supports up to 512 MB 8 banks of DDR2/DDR3 (DLL off only)/ DDR3L (DLL off only)/ LPDDR1/LPDDR2/ LPDDR3, including "on-the-fly" encryption/decryption paths

– 8-bit SLC/MLC NAND controller with up to 32-bit error correction code (PMECC)

If you have any needs, please contact Mr. Zhong:

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Tel: +86-13530718420

Email: szmyxdz@163.com

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