Shenzhen Meiyuxin Technology Co., Ltd. [distributing TI processors] supplies AM6546BACDXA quad-core Arm® Cortex®-A53 and dual-core Arm Cortex-R5F Sitara™ processors with Gigabit PRU-ICSS Quality assurance! ! !

Product Description:

The AM6546BACDXA device combines four or two Arm Cortex-A53 cores with a dual Arm Cortex-R5F MCU subsystem (including features designed to help customers achieve their end product functional safety goals) and a three-gigabit industrial communication subsystem (PRU_ICSSG ) combined to enable SoC-enabled high-performance industrial control with industrial connectivity and processing for functional safety applications. The AM65xx is currently undergoing certification evaluation by TÜV SÜD in accordance with the requirements of the IEC 61508 standard.

The four Arm Cortex-A53 cores in the AM6546BACDXA are distributed across two dual-core clusters with shared L2 memory to create two processing lanes. The two Arm Cortex-A53 cores in the AM652x are available as a single dual-core cluster and two single-core cluster options. Extensive ECC is included in on-chip memory, peripherals, and interconnects to ensure reliability. Features are included throughout the SoC to help customers design their functional safety goals (pending TÜV SÜD evaluation results). In addition to the granular firewall managed by the DMSC, cryptographic acceleration and secure boot are available on some AM654x and AM652x devices.

The AM6546BACDXA Arm Cortex-A53 RISC CPU with Arm Neon™ extensions enables programmability, while the dual Arm Cortex-R5F MCU subsystem can be used as two cores for general use or in lockstep mode to help meet the requirements of functional safety applications. need. The PRU_ICSSG subsystem can be used to provide up to six industrial Ethernet ports such as Profinet IRT, TSN, Ethernet/IP or EtherCAT, or for standard Gigabit Ethernet connections.

Features:

Memory Subsystem:

• Up to 2MB of on-chip L3 RAM (with SECDED)

• Multicore Shared Memory Controller (MSMC)

– Up to 2MB (2 banks × 1MB) of SRAM with SECDED

• Shared coherent Level 2 or Level 3 memory-mapped SRAM

• Shared coherent L3 cache

– 256-bit processor port bus and 40-bit physical address bus

– Coherent unified bidirectional interface for connection to processor or device host

– L2, L3 cache warmup and post flush

– Bandwidth management with starvation limit

– A base setup main interface

– Single external memory master interface

– Support distributed virtual system

– Supports internal DMA engine - Data Routing Unit (DRU)

– ECC error protection

• DDR Subsystem (DDRSS)

– Supports DDR4 memory types up to DDR-1600

– 32-bit data bus and 7-bit SECDED bus

– 8 GB of total addressable space

• General Purpose Memory Controller (GPMC)

SafeTI™ Semiconductor Components:

• Designed for functional safety applications

• Developed according to the requirements of the IEC 61508 standard

• System integrity up to SIL-3

• For MCU safety islands, include enough diagnostics to meet SIL-2 random fault integrity requirements

• For the rest of the SoC, include enough diagnostics to meet the random fault integrity requirements of SIL-2

• In addition, adequate architectural metrics need to be configured to enable SIL-3 execution considering specific safety concepts (eg software reciprocal comparison)

• Provide functional safety manual

• Safety-related certifications

– TÜV SÜD Component Level Functional Safety Certification [Certifying]

• Functional safety features:

– ECC or parity for compute-critical memory and internal bus interconnects

– Firewall to help prevent interference (FFI)

• Built-in self-test (BIST) for CPU, high-end timers, and on-chip RAM

– Hardware fault injection support for diagnostic tests

– Error Signaling Module (ESM) for catching functional safety-related errors

– Voltage, temperature and clock monitoring

– Windowed and non-windowed watchdog timers in multiple clock domains

• MCU Island

– Isolated dual-core Arm® Cortex®-R5F microprocessor subsystem,

– Independent voltage, clock, reset and dedicated peripherals

– Internal MCSPI connection to rest of SoC