Shenzhen Meiyuxin Technology Co., Ltd. 【Distribution of automotive processor chips】Supply TDA4VE88TGAALZRQ1 Automated parking and driving assistance through AI, automotive system-on-chip with visual preprocessing and GPU Quality assurance Brand new and original Support third-party platform testing!

Product Description:

Based on the evolved Jacinto™ 7 architecture, the TDA4VE88TGAALZRQ1 processor family targets smart vision camera applications and builds on TI's extensive market knowledge accumulated over more than a decade of vision processor market leadership. The TDA4AL provides high-performance computing for traditional and deep learning algorithms at an industry-leading power/performance ratio, with a high level of system integration for scalability and lower cost for advanced vision camera applications. Key cores include next-generation DSPs with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, the latest Arm and GPU processors for general-purpose computing, integrated next-generation imaging subsystems (ISPs), video codecs and stand-alone MCU Island. All of this is protected by automotive-grade safety and security hardware accelerators.

TDA4VE88TGAALZRQ1 Key Performance Core Overview: "C7x" next-generation DSP combines TI's industry-leading DSP and EVE cores into a single higher-performance core and adds floating-point vector computation for backward compatibility with legacy code , while simplifying software programming. When operating at a typical automotive worst-case junction temperature of 125°C, the new "MMA" deep learning accelerator can achieve up to 8 TOPS of performance in the industry's lowest power envelope. Dedicated vision hardware accelerators provide vision pre-processing without impacting system performance.

General Computing Cores and Integration Overview: Arm® Cortex®-A72's independent dual-core cluster configuration facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems support low-level, timing-critical processing tasks, leaving applications unencumbered by the Arm® Cortex®-A72 core. TI's 7th generation ISP builds on existing world-class ISPs with the flexibility to handle a wider sensor suite, support for higher bit depths, and features for analytics applications. Integrated diagnostics and security features support operations up to ASIL-D levels, while integrated security features protect data from modern attacks. The CSI2.0 port supports multi-sensor input. For further integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island, eliminating the need for an external system microcontroller.

Features:

Processor Core:

• Two C7x floating-point vector DSPs up to 1.0 GHz, 160 GFLOPS, 512 GOPS

• Deep Learning Matrix Multiplication Accelerator (MMA), up to 8 TOPS at 1.0 GHz (8b)

• Vision Processing Accelerator with Image (VPAC) Signal Processor (ISP) and Multiple Vision Assist Accelerators

• Depth and Motion Processing Accelerator (DMPAC)

• Dual 64-bit Arm® Cortex®-A72 microprocessors up to 2 GHz subsystem

– 1MB shared L2 cache per dual-core Cortex®-A72 cluster

– 32KB L1 DCache and 48KB L1 ICache each Cortex®-A72 core

• Up to six Arm® Cortex®-R5F MCUs, up to 1.0 GHz

– 16K I-Cache, 16K D-Cache, 64K L2 TCM

– Two Arm® Cortex®-R5F MCU subsystems in an isolated MCU

– Arm® Cortex®-R5F MCU split in four (TDA4VE) or two (TDA4AL/TDA4VL) general-purpose computing

• GPU IMG BXS-64-4, 256kB cache, up to 800MHz, 50 GFLOPS, 4 GTexels/s (TDA4VE and TDA4VL) close to maximum processing entitlement

Memory Subsystem:

• Up to 4MB of on-chip L3 RAM with ECC and coherency

– ECC error protection

– shared coherent cache

– Supports internal DMA engine

• Up to two External Memory Interface (EMIF) modules with ECC

– Support LPDDR4 memory type

– Supports speeds up to 4266 MT/s

– Two (TDA4VE) or one (TDA4AL/TDA4VL) 32-

1-bit data bus with inline ECC up to 17 GB/sEMIF

• General Purpose Memory Controller (GPMC)

• On-chip SRAM in one (TDA4AL/TDA4VL) or two (TDA4VE) 512KBMAIN domains, protected by ECC