Shenzhen Meiyuxin Technology Co., Ltd. [TI Agent] SN65DSI83TPAPRQ1 LVDS Interface Integrated Circuit Bridge! ! !

Product Description:

The SN65DSI83TPAPRQ1 DSI-to-LVDS bridge features a single-lane MIPI D-PHY receiver front-end configuration with 4 lanes per lane, each lane operating at 1Gbps, with a maximum input bandwidth of 4Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 24bpp RGB888 video streams and converts the formatted video data streams to LVDS outputs with a pixel clock ranging from 25MHz to 154MHz, providing single-link LVDS with 4 data channel).

The SN65DSI83TPAPRQ1 device supports resolutions up to WUXGA 1920 × 1200 (60 frames per second, 24bpp with reduced blanking). The SN65DSI83TPAPRQ1 device is also suitable for applications using 60fps 1366 × 768/1280 × 800 (18bpp and 24bpp). The device implements partial line buffering to accommodate data flow mismatch between DSI and LVDS interfaces.

The SN65DSI83TPAPRQ1 device is packaged in a small-outline 10mm × 10mm HTQFP (0.5mm pitch) package and operates over the –40ºC to +105ºC temperature range.

Product Features:

• Qualified for automotive applications

• Offers the following AEC-Q100 qualified characteristics:

• Device Temperature Grade 2: Ambient operating temperature range of –40°C to +105°C

• Device HBM ESD Classification Level 3A

• Device CDM ESD classification level C6

• Implements MIPI® D-PHY Version 1.00.00 Physical Layer Front End and Display Serial Interface (DSI) Version 1.02.00

• Single-lane DSI receiver configurable with 1, 2, 3 or 4 D-PHY data lanes per lane, operating at up to 1Gbps per lane

• Supports 18bpp and 24bpp DSI video streams in RGB666 and RGB888 formats

• Maximum resolution up to 60fps WUXGA 1920 × 1200 (18bpp and 24bpp color with simplified blanking). Suitable for 60fps 1366 × 768/1280 × 800 (18bpp and 24bpp)

• Output for single-link LVDS

• Supports single-lane DSI to single-link LVDS mode of operation

• LVDS output clock range from 25MHz to 154MHz

• LVDS pixel clock can be free running continuous D-PHY clock or external reference clock (REFCLK)

• 1.8V main VCC supply

• Low power features including shutdown mode, low LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support

• LVDS lane swap (SWAP) for simplified printed circuit board (PCB) routing, LVDS pin order reverse feature

• Packaged in a 64-pin 10mm × 10mm HTQFP (PAP) PowerPAD™ IC package

Applications:

• Infotainment head unit with integrated display

• Head unit infotainment with remote display

• Infotainment Rear Seat Entertainment

• Hybrid vehicle cluster

• Portable navigation device

• Navigation

• Industrial Human Machine Interface (HMI) and Displays