The SAK-TC277TP-64F200N DC belongs to the first generation of Aurix TC27xT products. Its innovative multi-core architecture is based on up to three independent 32-bit TriCore CPUs, designed to meet the highest safety standards while dramatically increasing performance. Equipped with a 200 MHz TriCore, 5V or 3.3V single-voltage supply, and a powerful General Purpose Timer Module (GTM), the TC27xT family is designed to reduce complexity, achieve best-in-class power consumption, and save significant cost.

Features:

Multifunctional On-Chip Peripheral Unit

– Four asynchronous/synchronous serial channels (ASCLIN) supporting hardware LIN (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud

– Four queued SPI interface lanes (QSPI) with up to 50 Mbit/s master-slave capability

– High Speed Serial Link (HSSL) for serial interprocessor communication up to 320 Mbit/s

– Two serial microsecond bus interfaces (MSC) for serial port expansion to external power devices

– A MultiCAN+ module with 4 CAN nodes and 256 freely assignable efficient message objects Data processing via FIFO buffering and gateway data transfer

– 10 Single Edged Nibble Transport (SENT) lanes for connecting sensors

– One FlexRayTM module (E-Ray) with 2 channels supports V2.1

– A Generic Timer Module (GTM) that provides a powerful set of digital signal filtering and timer functions for autonomous and complex I/O management

– One capture/compare 6 module (two cores CCU60 and CCU61)

– One general purpose 12 timer unit (GPT120)

– Three-channel peripheral sensor interface according to V1.3 (PSI5)

– Peripheral Sensor Interface (PSI5-S) with Serial PHY

– Optional Inter-Integrated Circuit Bus Interface (I2C) Compliant with V2.1

– Optional IEEE802.3 Ethernet MAC with RMII and MII interface (ETH)

• Versatile Successive Approximation ADC (VADC)

– Cluster of 8 independent ADC cores

– Input voltage range from 0 V to 5.5 V (ADC power supply)

• Delta-Sigma Analog-to-Digital Converter (DSADC)

– Six channels

• Digitally programmable I/O ports

• On-chip debug support OCDS Level 1 (CPU, DMA, on-chip bus)

• Multicore debug, real-time trace and calibration

• Four/five-wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface

• Power management system and on-chip voltage regulator

• Clock generation unit with system PLL and Flexray PLL

• Embedded voltage regulator