The SPC58NH92C5RMI0Xmicrocontroller belongs to a family of devices superseding the SPC58x family. SPC58EHx, SPC58NHx builds on the legacy of the SPC5x family, while introducing new features coupled with higher throughput to provide substantial reduction of cost per feature and significant power and performance improvement (MIPS per mW).

AEC-Q100 qualified

High performance e200z4 triple core:

32-bit Power Architecture technology CPU

Core frequency as high as 200 MHz

Variable Length Encoding (VLE)

Floating Point, End-to-End Error Correction

10496 KB (10240 KB code Flash + 256 KB data Flash) on-chip Flash memory:

Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation

Supports read while read between the two code Flash partitions

Hardware support for Flash context switching (for FOTA with multi software versions)

1088 KB on-chip general-purpose SRAM (in addition to 192 KB core local data RAM):

64 KB in CPU_0, 64 KB in CPU_1 and 64 KB in CPU_2

224 KB HSM dedicated Flash memory (192 KB code + 32 KB data)

Multi-channel direct memory access controller (eDMA):

One eDMA with 64 channels

One eDMA with 16 channels

One interrupt controller (INTC)

Comprehensive new generation ASIL-D safety concept:

ASIL-D of ISO 26262

One CPU channel in lockstep

Logic BIST

FCCU for collection and reaction to failure notifications

Memory BIST

Cyclic redundancy check (CRC) unit

Memory Error Management Unit (MEMU) for collection and reporting of error events in memories