OMAPL138EZCED4 The device's DSP core uses a L2 cache-based architecture. The level 1 program cache (L1P) is a 32KB direct mapped cache and the level 1 data cache (L1D) is a 32KB 2-way set associative cache. The Level 2 Program Cache (L2P) consists of 256KB of memory shared between program space and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Although ARM9 and other hosts in the system can access DSP L2, an additional 128KB of RAM shared memory is provided for other hosts to avoid affecting DSP performance.

Product parameters:

Product Category: Digital Signal Processors and Controllers - DSP, DSC

RoHS: Details

Products: DSPs

Series: OMAP-L138

Brand name: OMAP

Installation style: SMD/SMT

Package / Box: PBGA-361

Core: ARM926EJ-S, C674x

Number of cores: 2 Core

Maximum Clock Frequency: 456 MHz, 456 MHz

L1 cache instruction memory: 16 kB, 32 kB

L1 cache data memory: 16 kB, 32 kB

Program memory size: 32 kB

Data RAM size: 8 kB

Operating supply voltage: 1.3 V

Minimum working temperature: - 40 C

Maximum working temperature: + 105 C

Data bus width: 16 bit, 32 bit

Data ROM size: 64 kB

Height: 0.94mm

I/O Voltage: 1.8V, 3.3V

Manual Type: Fixed/Floating Point

Interface Type: I2C, Parallel, SPI, USB

Length: 13mm

MFLOPS: 2746 MFLOPS

Humidity Sensitivity: Yes

Number of Timers/Counters: 3 Timer

Processor Family: OMAP

Product Type: DSP - Digital Signal Processors & Controllers

Subcategory: Embedded Processors & Controllers

Supply Voltage - Max: 1.35 V

Supply Voltage - Min: 1.25 V

Watchdog Timer: Watchdog Timer

Width: 13mm

Unit weight: 789.400 mg