Shenzhen Meiyuxin Technology Co., Ltd. [specializes in MICRON chips] MT28EW01GABA1HPC-0SIT

memory NOR flash memory EW-SERIES FLASH NOR SLC 64MX16 LBGA quality assurance 

Brand new original! ! !

Product Description:

MT28EW01GABA1HPC-0SIT The device is an asynchronous, unified block, parallel NOR flash memory

 device. READ, ERASE, and PROGRAM operations are performed using a single low-voltage power 

supply. After power up, the device defaults to read array mode. The main memory array is divided into 

uniform blocks that can be erased independently to preserve valid data while clearing old data. 

Program and erase commands are written to the command interface of the memory. 

The on-chip program/erase controller handles all the special operations required to update memory

 contents by taking steps to simplify the process of programming or erasing memory. An end can 

detect program or erase operations and can identify any error conditions. The command set required

 to control the device complies with the JEDEC standard.

MT28EW01GABA1HPC-0SIT The device supports asynchronous random reads from all blocks and page 

reads in bulk. It also features an internal program buffer that can program 512 words with a single command 

sequence for increased throughput. A 128-word block of extended memory overlaps address with array block 0. 

Users can program this extra space and then secure it to permanently protect content. The device also has 

different levels of hardware and software protection to protect blocks from unwanted modification.

Features:

• Single Level Cell (SLC) technology

• Density: 512Mb

• voltage

– VCC = 2.7–3.6V (Program, Erase, Read)

– VCCQ = 1.65 - VCC (I/O buffer)

• Asynchronous random/page read

– Page size: 16 words or 32 bytes

– Page access: 20ns

– Random access: 95ns (VCC = VCCQ = 2.7-3.6V)

– Random access: 100ns (VCCQ = 1.65-VCC)

• Buffer program (512 word program buffer)

– 2.0 MB/s (TYP) when using fully buffered programs

– 2.5 MB/s (TYP) program (VHH) when using accelerated buffer

• Word/byte program: 25us per word (TYP)

• Block Erase (128KB): 0.2s (TYP)

• memory organization

– Uniform blocks: 128KB or 64KW each

– x8/x16 data bus

• Program/erase suspend and resume capability

– Read pause operation from another block during program

– Read or program another block suspend operation during ERASE

• Unlock bypass, block erase, chip erase and write buffer capabilities

• BLANK CHECK operation to verify erased blocks

• Cyclic redundancy check (CRC) operation to verify program mode

• VPP/WP# protection

– Protects the first or last block, regardless of the block protection setting

• Software protection

– Volatility protection

– Non-volatile protection

- password protection

• Extended memory block

– 128-word (256-byte) blocks for permanent, secure

- programmed or locked at the factory or by

• JESD47 Compliant

– 100,000 (minimum) ERASE cycles per block

– Data retention: 20 years (typical)

• pack

– 56-pin TSOP, 14 x 20mm (JS)

– 64-ball LBGA, 11 x 13mm (PC)

– 56-ball VFBGA, 7 x 9mm (PN)

• RoHS Compliant Halogen Free Packaging

• Operating temperature

– Environmental: –40°C to +85°C