Shenzhen Meiyuxin Technology Co., Ltd. [distribution memory] MT53D512M32D2DS-046 AAT:D LPDDR4 memory IC quality assurance brand new original! ! !

Product parameters:

This data sheet specifies the operation of unified LPDDR4 and LPDDR4X products and first describes the specific requirements for LPDDR4X 0.60V VDDQ operation. When using the product as an LPDDR4 device.

• Ultra-low voltage core and I/O supplies

– VDD1 = 1.70–1.95V; 1.80V nominal

– VDD2 = 1.06–1.17V; 1.10V nominal

– VDDQ = 1.06–1.17V; 1.10V nominal or low VDDQ = 0.57–0.65V; 0.60V nominal

• Frequency Range

– 2133–10 MHz (data rate range: 4266–20 Mb/s/pin)

• 16n prefetch DDR architecture

• 8 internal banks per channel for concurrent operation

• Single data rate CMD/ADR input

• Bidirectional/differential data strobe per byte lane

• Programmable Read and Write Latency (RL/WL)

• Programmable and instant burst length (BL =16, 32)

• Directed per-bank refresh and easy command scheduling for concurrent bank operations

• Up to 8.5 GB/s per chip

• On-chip temperature sensor to control self-refresh rate

• Partial Array Self Refresh (PASR)

• Selectable output drive strength (DS)

• Clock stop capability

• RoHS Compliant "Green" Packaging

• Programmable VSS (ODT) termination

• AEC-Q100 option mark

• VDD1/VDD2/VDDQ: 1.80V/1.10V/1.10V or 0.60V D

• Array configuration

– 512M×16 (1 channel×16 I/O) 512M16

– 512M × 32 (2 channels × 16 I/O) 512M32

– 1024M×32 (2 channels×16 I/O) 1024M32

• Device Configuration

– 512M16 × 1 chip in package D1

– 512M16 × 2 chips in package D2

– 512M16 × 4 chips in D4 package

• FBGA "green" package

– 200-ball WFBGA (10mm × 14.5mm × 0.8mm, Ø0.35 SMD) DS

– 200-ball VFBGA (10mm × 14.5mm × 0.95mm, Ø0.35 SMD) DT

• Speed class, cycle time

– 535ps @ RL = 32/36 -053

– 468ps @ RL = 36/40-046

• special options

– Automotive grade (package level burn-in) A

• range of working temperature

– –40°C to +95°C IT

– –40°C to +105°C AT

– –40°C to +125°C UT1

• Revision: D