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DRA746APGABCQ1 Arm Cortex-A15 SoC processor

Time:2023-03-21   Views:

Shenzhen Meiyuxin Technology Co., Ltd.【Supply Microprocessor】DRA746APGABCQ1 1.5GHz Dual-Core Arm Cortex-A15 SoC Processor with Graphics and DSP for Car Infotainment and Instrument Clusters for Sale Quality Assurance New Original! ! !


Product Description:

The DRA746APGABCQ1 (Jacinto 6) infotainment applications processor is designed to meet the intense processing performance demands of modern in-vehicle infotainment experiences.


The DRA746APGABCQ1 device enables original equipment manufacturers (OEMs) and original design manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. The Jacinto 6 device achieves high processing performance through its highly flexible fully integrated mixed processor solution. In addition, these devices incorporate a highly integrated peripheral set in addition to programmable video processing.


The DRA746APGABCQ1 dual-core Arm® Cortex®-A15 RISC CPU with Arm® Neon™ extensions, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with 1 or more EVEs) provides programming capabilities. With Arm, developers can reduce system software complexity by separating control functions from other algorithms programmed on the DSP and coprocessors.


Features:

• Architecture designed for infotainment applications

• Supports video, image and graphics processing

– Full HD video (1920 × 1080p, 60fps)

– Multiple video inputs and video outputs

– 2D and 3D graphics

• Dual-core Arm® Cortex®

-A15 Microprocessor Subsystem

• C66x floating-point VLIW DSP up to two

– Object code fully compatible with C67x and C64x+

– Up to 32 16 x 16-bit fixed-point multiplications per cycle

• On-chip L3 RAM up to 2.5MB

• Level 3 (L3) and Level 4 (L4) interconnects

• Two DDR2/DDR3/DDR3L memory interface (EMIF) modules

– Support up to DDR2-800 and DDR3-1066

– Each EMIF supports up to 2GB

• Dual-core Arm® Cortex®

-M4 Image Processing Unit (IPU)

• Up to two Embedded Vision Engines (EVEs)

• IVA subsystem

• Display subsystem

– Display controller with DMA engine and up to 3 pipelines

– HDMI™ Encoder: Compatible with HDMI 1.4a and DVI 1.0

• Video Processing Engine (VPE)

• 2D graphics accelerator (BB2D) subsystem

– Vivante® GC320 core

• Dual-core PowerVR® SGX544 3D GPU

• Three Video Input Port (VIP) modules

– Supports up to 10 multiplexed input ports

• General Purpose Memory Controller (GPMC)

• Enhanced Direct Memory Access (EDMA) Controller

• 2-port Gigabit Ethernet (GMAC)

• 16 32-bit general-purpose timers 32-bit MPU watchdog timer

• Five inter-integrated circuits (I2C™) ports

• HDQ™/Single Wire® interface

• SATA interface

• MediaLB® (MLB) subsystem

• 10 configurable UART/IrDA/CIR modules

• Four Multichannel Serial Peripheral Interfaces (McSPIs)

• Quad SPI (QSPI)

• Eight Multichannel Audio Serial Port (McASP) modules

• SuperSpeed USB 3.0 dual role device

• Three Hi-Speed USB 2.0 dual-role devices

• Four Multimedia Card/Secure Digital/Secure Digital I/O (MMC™/ SD®/SDIO)

• PCI-Express®3.0 subsystem with two 5Gbps lanes

– One Gen 2 compatible dual channel port

– or two Gen 2 compatible single-lane ports

• Dual Controller Area Network (DCAN) module

– CAN 2.0B protocol

• Up to 247 general-purpose I/O (GPIO) pins

• Real Time Clock Subsystem (RTCSS)

• Device Security Features

– Hardware cryptographic accelerator and DMA

– Firewall

– JTAG® lock

– security key

– Secure ROM and boot

• Power, Reset and Clock Management (PRCM)

• Supports on-chip debugging with CTool technology

• 28nm CMOS technology

• 23mm × 23mm, 0.8mm pitch, 760-pin BGA(ABC)


Application:

• Human Machine Interface (HMI)

• navigation

• Digital and analog radios

• Rear seat entertainment system

• Multimedia playback

• Internet browsing capability

• ADAS integration

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If you have any needs, please contact Mr. Zhong:

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