Shenzhen Meiyuxin Technology Co., Ltd [Automotive Processor Supplier] Supply DRA821U4TCBALMRQ1 Automotive Gateway SoC with Dual-Core Arm® Cortex®-A72, Quad-Core Cortex-R5F, Quad-Port Ethernet Switch, PCIe! ! !

DRA821U4TCBALMRQ1 Product Description:

The Jacinto™ DRA821x processors are based on the Armv8 64-bit architecture and are optimized for gateway systems with cloud connectivity. A system-on-chip (SoC) design reduces system-level cost and complexity through integration, especially the system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features meet ASIL-D and SIL-3 certification requirements. Real-time control and low-latency communications are supported by PCIe controllers and TSN-enabled Gigabit Ethernet switches.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle simple, timing-critical processing tasks, shielding the Arm® Cortex®-A72 core from advanced and cloud-based applications.

The Jacinto DRA821x processors also incorporate the concept of extended MCU (eMCU) domains. This domain is a subset of processors and peripherals on the MAIN domain, designed to achieve higher functional safety, such as ASIL-D/SIL-3. The functional block diagram highlights which IP is included in the eMCU.

Features:

Processor core:

• Dual-core 64-bit Arm® Cortex®-A72 microprocessor subsystem, performance Capable of up to 2.0GHz, 24K DMIPS

– 1MB L2 shared cache per dual-core Cortex®-A72 cluster

– Each A72 core has 32KB L1 data cache and 48KB L1 instruction cache

• 4x Arm® Cortex®-R5F MCUs, performance up to 1.0GHz with selectable lockstep operation, 8K DMIPS

– 32K instruction cache, 32K data cache, 64K L2 TCM

– 2 x Arm® Cortex®-R5F MCUs in isolated MCU subsystem

– 2 Arm® Cortex®-R5F MCUs in the general compute partition

Memory Subsystem:

• 1MB of on-chip L3 RAM (with ECC and coherency)

– ECC error protection

– Shared coherent cache

– Supports internal DMA engine

• External memory interface (EMIF) block (with ECC)

– Support for LPDDR4 memory type compliant with JESD209-4B specification. (Byte mode LPDDR4 memories or memories with more than 17 row address bits are not supported)

– Supports speeds up to 3200MT/s

– 32-bit and 16-bit data bus with inline ECC bus, data rate up to 12.8GB/s

• General Purpose Memory Controller (GPMC)

• 512KB of on-chip SRAM in MAIN domain, protected by ECC

DRA821U4TCBALMRQ1  Applications:

• Automotive gateway

• Vehicle calculations

• Body Control Module

• Telematics control unit

• V2X/V2V

• Factory Automation Gateway

• communication device

• Industrial transport

• Building automation gateway