Shenzhen Meiyuxin Technology Co., Ltd. has a large number of off-the-shelf [supply microprocessors] DRA829JMTGBALFRQ1 8-port Ethernet and 4-port PCIe switches. Quality assurance, brand new and original, support third-party platform testing! ! !

Product Description:

DRA829JMTGBALFRQ1 Jacinto™ 7 The DRA829 processor is based on the Arm®v864 architecture and provides advanced system integration to reduce system cost for automotive and industrial applications. Integrated diagnostics and functional safety features meet ASIL-B/C or SIL-2 certification/requirements. An integrated microcontroller (MCU) island eliminates the need for an external system MCU. The device features a Gigabit Ethernet switch and PCIe hub to support network use cases that require large amounts of data bandwidth. Up to four Arm Cortex-R5F subsystems manage low-level, timing-critical processing tasks and keep the Arm Cortex-A72 independent of the application. A dual-core cluster configuration of the Arm Cortex-A72 facilitates multi-OS applications with very low software hypervisor requirements.

Product parameters:

Processor core:

• Dual-core 64-bit Arm® Cortex®-A72 microprocessor subsystem with performance up to 2.0GHz

– 1MB L2 shared cache per dual-core Arm® Cortex®-A72 cluster

– Each Cortex®-A72 core has 32KB L1 data cache and 48KB L1 instruction cache

• Six Arm® Cortex®-R5F MCUs with performance up to 1.0GHz

– 16K instruction cache, 16K data cache, 64K L2 TCM

– Two Arm® Cortex®-R5FMCUs in the isolated MCU subsystem

– Four Arm® Cortex®-R5FMCUs in the general compute partition

• Deep Learning Matrix Multiplication Accelerator (MMA) with performance up to 8TOPS (8b) at 1.0GHz

• C7x floating-point vector DSP with performance up to 1.0GHz, 80GFLOPS, 256GOPS

• Two C66x floating-point DSPs with performance up to 1.35GHz, 40GFLOPS, 160GOPS

• 3D GPU PowerVR® Rogue 8XE GE8430 with performance up to 750MHz, 96GFLOPS, 6Gpix/s

Memory Subsystem:

• Up to 8MB of on-chip L3 RAM (with ECC and coherency)

– ECC error protection

– Shared coherent cache

– Supports internal DMA engine

• External memory interface (EMIF) block (with ECC)

– Supports LPDDR4 memory type

– Supports speeds up to 4266MT/s

– 32-bit data bus with inline ECC, data rate up to 14.9GB/s

• General Purpose Memory Controller (GPMC)

• 512KB of on-chip SRAM in the main domain, protected by ECC

Display subsystem:

• 1 eDP/DP interface with multi-monitor support (MST)

– HDCP1.4/HDCP2.2 High Bandwidth Digital Content Protection

• 1 DSI TX (up to 2.5K)

• Up to 2 DPI

Video Acceleration:

• Ultra HD video, 1 (3840 × 2160p, 60fps) or 2 (3840 × 2160p, 30fps) H.264/H.265 decoding

• Full HD video, 4 (1920 × 1080p, 60fps) or 8 (1920 × 1080p, 30fps) H.264/H.265 decoding

• Full HD video, 1 (1920 × 1080p, 60fps) or up to 3 (1920 × 1080p, 30fps) H.264 encoding

Functional safety:

• Target functional safety compliance (on select device variants)

– Specifically developed for functional safety applications

– Documentation helps make ISO 26262 functional safety system designs meet ASIL-D/SIL-3 requirements

– System functionality meets ASIL-D/SIL-3 requirements

– For MCU domain, hardware integrity meets ASIL-D/SIL-3 requirements

– For primary domain, hardware integrity meets ASIL-B/SIL-2 requirements

– Safety-related certifications

• ISO 26262 certification planned for

• AEC-Q100 qualified (part numbers ending in Q1)