Shenzhen Meiyuxin Technology Co., Ltd [FBGA agent] brand new original LCMXO2-1200HC-4MG132C FPGA - Field Programmable Gate Array 1280 LUTs 105 I/O 3.3V! ! !

Product Description:

The LCMXO2-1200HC-4MG132C MachXO2™ family of ultra-low-power, instant-on, non-volatile PLDs has six devices and densities ranging from 256 to 6864 look-up tables (LUTs). In addition to low-cost LUT-based programmable logic, these devices feature embedded block RAM (EBR), distributed RAM, user flash memory (UFM), phase-locked loop (PLL), pre-engineered source synchronous I/O support, advanced configuration support, including The ability to dual-boot commonly used and enhanced version features such as SPI controller, I2C controller and timer/counter. These features allow these devices to be used in low-cost, high-volume consumer and system applications.

The LCMXO2-1200HC-4MG132C MachXO2 device is designed on a 65 nm non-volatile low-power process. The device architecture has features such as programmable low-swing differential I/Os and the ability to dynamically power down banks of I/Os, on-chip PLLs, and oscillators. These features help manage static and dynamic power consumption resulting in low static power consumption for all members of the family.

The LCMXO2-1200HC-4MG132C MachXO2 device is available in two versions: ultra-low-power (ZE) and high-performance (HC and other) devices. Ultra-low power devices are available in three speed grades –1, –2, and –3, with –3 being the fastest. Likewise, high-performance devices are available in three speed grades: –4, –5, and –6, with –6 being the fastest. HC devices have internal linear regulators supporting external VCC supply voltages of 3.3 V or 2.5 V. Only ZE and HE devices accept 1.2 V as an external VCC supply voltage. Functionally and pin-to-pin compatible with equipment except for three mains voltage categories (ZE, HC and HE).

The LCMXO2-1200HC-4MG132C MachXO2 PLD is available in a wide range of advanced halogen-free packages ranging from space-saving 2.5 mm x 2.5 mm WLCSP to 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same package. Table 1.1 shows LUT density, package and I/O options, and other key parameters. Predesigned source synchronous logic implemented in the MachXO2 device family supports a wide range of interface standards including LPDDR, DDR, DDR2, and 7:1 gear ratios for display I/O.

The LCMXO2-1200HC-4MG132C MachXO2 device provides enhanced I/O features such as drive strength control, slew rate control, PCI compatibility, bus keeper latches, pull-up resistors, pull-down resistors, open-drain outputs, and thermal sockets. Pull-up, pull-down and bus-keeper functions are controllable on a "per-pin" basis.

A user-programmable internal oscillator is included with MachXO2 devices. The oscillator's clock output can be divided by a timer/counter to clock input functions such as LED control, keypad scanner and similar state machines.

The LCMXO2-1200HC-4MG132C MachXO2 device also offers flexible, reliable, and secure configuration from on-chip flash memory. These devices can also be accessed from external SPI flash or by an external configuration host via the JTAG test access port or via the I2C port. In addition, MachXO2 devices support dual-boot capability (using external flash memory) and Remote Field Upgrade (TransFR) capability.

LCMXO2-1200HC-4MG132C Lattice offers a variety of design tools that allow complex designs to be effectively implemented using the MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice Design Tools Place and route designs in MachXO2 devices using synthesis tool output with user-specified preferences and constraints. These tools extract timing from routing and back-inject it into the design for timing verification.

LCMXO2-1200HC-4MG132C Lattice offers a number of pre-designed IP (Intellectual Attributes) LatticeCORE™ blocks, including some freely licensed reference designs, optimized for the MachXO2 PLD family. By using these configurable soft IP cores as standardized blocks, users are free to focus on unique aspects of their designs, increasing their productivity.