Shenzhen Meiyuxin Technology Co., Ltd. Supplies XC6SLX9-2TQG144C Imported Chip FPGA - Field Programmable Gate Array Brand New Original Authentic! ! !

Product Description:

The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.

Spartan-6 Family:

Spartan-6 LX FPGA: Logic optimized

Spartan-6 LXT FPGA: High-speed serial connectivity

Designed for low cost

Multiple efficient integrated blocks

Optimized selection of I/O standards

Staggered pads

High-volume plastic wire-bonded packages

Low static and dynamic power

45 nm process optimized for cost and low power

Hibernate power-down mode for zero power

Suspend mode maintains state and configuration with

multi-pin wake-up, control enhancement

Lower-power 1.0V core voltage (LX FPGAs, -1L only)

High performance 1.2V core voltage (LX and LXT

FPGAs, -2, -3, and -3N speed grades)

Multi-voltage, multi-standard SelectIO™ interface banks

Up to 1,080 Mb/s data transfer rate per differential I/O

Selectable output drive, up to 24 mA per pin

3.3V to 1.2V I/O standards and protocols

Low-cost HSTL and SSTL memory interfaces

Hot swap compliance

Adjustable I/O slew rates to improve signal integrity